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To study and simulate design of 4bit comparator IC 7485 using VHDL.


The7485 is a 4bit magnitude comparator that can be expanded to almost any length. It has three cascade inputs A>Bin, A<Bin and A=Bin. The four bit inputs are weighted (A0-A3) and (B0-B3), where A3&B3 are the most significant bits. The cascading outputs are A>Bout, A<Bout and A equ Bout. AGTBOUT=(A>B)+(A=B). AGTBIN AEQBOUT=(A=B). AEQBIN ALTBOUT=(A<B)+(A=B). ALTBIN


The IC 7485 Design is entered through VHDL.
Simulate the design by applying test vectors-a,b, a_gt_bin,a_lt_bin, and a_eq_bin and observing output x, y, z.
It is required to lock the pins and give timing constraints.
Implement the design by passing the design by various stages by mapping, time analysis and bit stream. For locking the pins write UCF file before implementation and guide the same through option set control files. Output of the implementation is .JED file, which can be directly programmed into target device FPGA.
The last step is programming in which the programme can physically download the architecture from computer to target device FPGA

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