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8085 Microprocessor Architecture
Post: #1

.ppt  TK2633-Lecture12-8085 Architecture-Introduction.ppt (Size: 787 KB / Downloads: 328)
8085 Microprocessor Architecture
 Intel 8085 CPU Block Diagram
 The 8085 Block Diagram
 Registers – hold temporary data.
 Instruction register (IR)– holds the currently executing instruction.
 Instruction Decoder (ID)- decodes the instruction. Once decoded, the instruction controls the remainder of the MPU, memory and IO through the timing and control block.
 The 8085 Block Diagram
 Temporary register- holds information from the memory or register array. An input of the ALU.
 Increment/Decrement address latch – It adds or subtracts one from any of other registers in register array.
Intel 8085 Pin Configuration
 Clock Pins
 8085 MPU has 3 pins that control or present the clock signal.
 X1 and X2 pins determine the clock frequency.
 CLK OUT is a TTL square-wave output clock.
 The CLOCK OUT is one-half the crystal frequency.
 8085 Pinout
 8085 μp consists of 16 signal pins use as address bus.
 Divide into 2 part: A15 – A8 (upper) and
AD7 – AD0 (lower).
 A15 – A8 : Unidirectional, known as ‘high order address’.
 AD7 – AD0 : bidirectional and dual purpose (address and data placed once at a time).
 AD7 – AD0 also known as ‘low order address’.
 To execute an instruction, at early stage AD7 – AD0 uses as address bus and alternately as data bus for the next cycle.
 The method to change from address bus to data bus known as ‘bus multiplexing’.
 8085 Pinout
 Group of signals consists of :
 Two control signals (‘RD’ – read; and ‘WR’ - write).
 Three status signals (IO/M, S1, and S0) to recognize nature of operation.
 ALE (Address Latch Enable) signal :
 active high signal - generated to show the start of 8085 operation.
 When transition 1-to-0: indicate that lines AD7-AD0 (AD7-AD0 = A7-A0) act as address lines.
ALE used to demultiplex address/data bus
 Control and Status Signals
 Signals:
 RD – Read (active low). To indicate that the I/O or memory selected is to be read and data are available on the bus.
 WR – Write: Active low. This is to indicate that the data available on the bus are to be written to memory or I/O ports.
 IO/M – To differentiate I/O operation of memory operations.
 ‘0’ - indicates a memory operation.
 ‘1’-indicates an I/O operation.
 IO/M combined with RD and WR to generate I/O and memory control signals.
 S1 dan S0: Status signals, similar to IO/M, can identify various operations as shown on the following table :
 Control and Status Signals.
 Interrupt Signals
 8085 μp has several interrupt signals as shown in the following table.
 Interrupt signals
 An interrupt is a hardware-initiated subroutine CALL.
 When interrupt pin is activated, an ISR will be called, interrupting the program that is currently executing.
 Interrupt signals
 INTR input is enabled when EI instruction is executed.
 The status of the RST 7.5, RST 6.5 and RST 5.5 pins are determined by both EI instruction and the condition of the mask bits in the interrupt mask register.
Interrupt Vectors
 A circuit that causes an RST4 instruction (E7) to be executed in response to INTR.
 When INTR is asserted, 8085 response with INTA pulse.
 During INTA pulse, 8085 expect to see an instruction applied to its data bus.
 RESET signal
 Following are the two kind of RESET signals:
 RESET IN: an active low input signal, Program Counter (PC) will be set to 0 and thus MPU will reset.
 RESET OUT: an output reset signal to indicate that the μp was reset (i.e. RESET IN=0). It also used to reset external devices.
RESET signal
Direct Memory Access (DMA)

 DMA is an IO technique where external IO device requests the use of the MPU buses.
 Allows external IO devices to gain high speed access to the memory.
 Example of IO devices that use DMA: disk memory system.
 HOLD and HLDA are used for DMA.
 If HOLD=1, 8085 will place it address, data and control pins at their high-impedance.
 A DMA acknowledgement is signaled by HLDA=1.
MPU Communication and Bus Timing
 The Fetch Execute Sequence :
 The μp placed a 16 bit memory address from PC (program counter) to address bus.
 Figure 4: at T1
– The high order address, 20H, is placed at A15 – A8.
– the low order address, 05H, is placed at AD7 - AD0 and ALE is active high.
– Synchronously the IO/M is in active low condition to show it is a memory operation.
 At T2 the active low control signal, RD, is activated so as to activate read operation; it is to indicate that the MPU is in fetch mode operation.
MPU Communication and Bus Timing
 T3: The active low RD signal enabled the byte instruction, 4FH, to be placed on AD7 – AD0 and transferred to the MPU. While RD high, the data bus will be in high impedance mode.
 T4: The machine code, 4FH, will then be decoded in instruction decoder. The content of accumulator (A) will then copied into C register at time state, T4.
Post: #2

.doc  Unit 1 Intorduction to 8085 Microprocessor.doc (Size: 452.5 KB / Downloads: 84)


Microprocessor is a Central Processing Unit (CPU) etched on a single chip. A single Integrated Circuit (IC) has all the functional components of a CPU namely Arithmetic Logic Unit (ALU), Control Unit and registers. The 8085 microprocessor is an 8-bit processor that includes on its chip most of the logic circuitry for performing computing tasks and for communicating with peripherals. The architecture of a microprocessor is to be learnt in terms of registers, memory addressing, addressing modes, instruction set, interfacing with memory and Input and Output (I/O) devices and interrupt handling. It is necessary to learn about the above mentioned concepts to write efficient assembly language programs, and to design microprocessor based systems. This unit gives you an overall idea about the microprocessors, the detailed discussion about 8085 architecture and interfacing of 8085 with Programmable Peripheral Interface (PPI) devices.

Learning Objectives

• To understand the basics and evolution of microprocessors
• To study about the functional components of 8085 in detail
• To discuss the different types of memory addressing schemes 0f 8085
• To learn the various addressing modes supported by 8085
• To study the various types of instructions provided by 8085
• To study the pin diagram and the signals of various pins of 8085
• To discuss about the timing and execution of instructions by 8085
• To understand the interrupt handling of 8085

Have you understood?

1. What are the major components of a digital computer?
2. What are the functional components of a CPU?
3. What is a microprocessor?

Evolution of Microprocessors

The first microprocessor was introduced in 1971 by Intel Corporation, U.S.A. It was a 4-bit microprocessor, the Intel 4004. The 4004 was introduced on November 15, 1971 and originally ran at a clock speed of 108KHz (108,000 cycles per second, or just over one-tenth a megahertz). The 4004 contained 2,300 transistors and was built on a 10-micron process. This means that each line, trace, or transistor could be spaced about 10 microns (millionths of a meter) apart. Data was transferred 4 bits at a time, and the maximum addressable memory was only 640 bytes. The 4004 was designed for use in a calculator but proved to be useful for many other functions because of its inherent programmability. In 1972, Intel introduced the 1st 8-bit processor, the Intel 8008. The Intel 8004 and 8008 both used Positive Channel Metal Oxide Semiconductor (PMOS) technology. In 1973 a more powerful and faster 8-bit processor, the Intel 8080 was introduced. It employed Negative Channel metal Oxide semiconductor (NMOS) technology.

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