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POWER OPTIMIZATION OF LINEAR FEEDBACK SHIFT REGISTER(LFSR)FOR LOW POWER BIST
Post: #1

Hi sir,
I want the code for the project called "POWER OPTIMIZATION OF LINEAR FEEDBACK SHIFT REGISTER(LFSR)FOR LOW POWER BIST..
Please send the code for this project... or atleast send the code for MODIFIED LFSR...

Thanking you sir
Post: #2
hi sir im doing btech n nw im final year student i want the code for power optimization of lfsr using low power bist please send to husjasmeen[at]gmail.com
Post: #3
i want code fr power optimisation in bist using lfsr.. plz send it to urfrndforever1992[at]yahoo.com
Post: #4
to get information about the topic "POWER OPTIMIZATION OF LINEAR FEEDBACK SHIFT REGISTER FOR LOW POWER

Reference: http://project-seminars.com/Thread-power...z2K00jnHKj"full report ppt and related topic refer the link bellow

http://project-seminars.com/Thread-power...-low-power
Post: #5
Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST



.doc  Power Optimization.doc (Size: 43 KB / Downloads: 20)

Abstract:

This paper proposes a low power Linear Feedback Shift Register (LFSR) for Test Pattern Generation (TPG) technique with reducing power dissipation during testing. The correlations between the consecutive patterns are higher during normal mode than during testing. The proposed approach uses the concept of reducing the transitions in the test pattern generated by conventional LFSR. The transition is reduced by increasing the correlation between the successive bits. A typical BIST architecture consists of a test pattern generator (TPG), usually implemented as a linear feedback shift register (LFSR), a test response analyzer (TRA), implemented as a multiple input shift register (MISR), and a BIST control unit (BCU), all implemented on the chip .The simulation result show that the interrupt controller benchmark circuit's testing power is reduced with respect to the power consumed during the testing carried by conventional LFSR.

Existing system:

Random single input change (RISC) which is used to generate low power test pattern generation.

Existing system disadvantages:

High power and ground noise caused by high switching during testing are serious problem where the supply connects are poor. Additional cost is also required.

Proposed system:

In this project, test patterns are generated externally by LFSR, which is inexpensive and high speed.0 LFSR is a circuit consists of flip-flops in series. LFSR is a shift register where output bit is an XOR function of some next vector input bits. The initial value of LFSR is called seed value. LFSR's seed value has a significant effect on energy consumption. The outputs that influence the input are called tap. A LFSR is represented by as polynomial, which is also known as characteristic polynomial used to determine the feedback taps, which determine the length of random pattern.

Introduction about the domain:

Due to the rapid advances in integration technologies, large-scale systems design - in short, due to the advent of core VLSI. The number of applications of integrated circuits in high-performance computing, telecommunications, and consumer electronics has been rising steadily, and at a very fast pace. Typically, the required computational power (or, in other words, the intelligence) of these applications is the driving force for the fast development of this field. This trend is expected to continue, with very important implications on VLSI and systems design. One of the most important characteristics of information services is their increasing need for very high processing power and bandwidth (in order to handle real-time video, for example).
 

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